This invention relates to a cache memory device storing both instructions and data.
In a computer system, a cache memory device is employed for the purpose of high-speed accesses for instruction fetch and for data access.
A cache memory of this kind is used as a data cache for storing data in addition to as an instruction cache in which instructions to be executed by a processor are stored. Though the cache memory device of this type can optimize capacity distribution between the instructions and data according to an application program, conventionally, an access requirement for instruction fetch and a data access requirement cannot be processed simultaneously because of a single port memory array thereof.
A type of cache memory device in which instruction cache and data cache are separated is also used. Though this type of cache memory device can process the access requirement for instruction fetch and data access requirement simultaneously, plural access requirements for instruction fetch cannot be processed simultaneously and plural data access requirements cannot be processed simultaneously because of the conventional single port memory array of the instruction cache and data cache.
In the computer system with a microprocessor construction, there are some cases, for executing an instruction, employing a microprocessor with an architecture of reduced instruction set computer (hereinafter referred to as RISC microprocessor). In the RISC microprocessor, an instruction set is fundamentally limited to instructions which can be executed in one cycle, thus the microprocessor executes the instructions successively every cycle. Also, a memory access instruction is limited to two kinds, for example, load instruction and store instruction.
In a processor unit in which the RISC microprocessor is connected with the cache memory device via an internal bus, the RISC microprocessor gives the cache memory device an instruction address to be successively generated by an increment of a program counter for instruction fetch and a data address to be generated for the data access based on load instruction and store instruction as respective access requirement addresses. When the microprocessor executes a sequence change instruction which requires a change in the instruction executing sequence, i.e., unconditional branch instruction, conditional branch instruction or the like, a branch address for instruction fetch in a branch target is given to the cache memory device as another access requiring address.
On the other hand, in a computer system with a multiprocessor construction in which a common system bus (external bus) is connected with plural processor units, each processor unit is generally provided with a bus supervisory device. For example, when data of the cache memory device in a processor unit is partially rewritten, it is necessary to invalidate data of the same address of the cache memory device in the other processor units according to a definition of cache protocol in order to maintain data consistency, i.e., coherency. Also, when the data of a common external memory device connected with the external bus is partially rewritten, the same operation is required. At the time, each bus supervisory device checks whether the cache memory device retains the data of a physical address supplied from the external bus. In other words, the bus supervisory device gives the physical address for regulating the data consistency as another access requiring address to the cache memory device. The coherency of the cache memory device in the multiprocessor system is referred to in J. Archibanld and J. L. Baer: "Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model" (ACM Trans. on Computer Systems, Vol. 4, No. 4, November 1986, pp. 273-298).
Each access requirement for instruction address, branch address, data address and physical address occurs independently. Therefore, four types of access requirements may occur simultaneously at the most.
With the conventional cache memory device in which the instruction cache and data cache are not separated, however, since the access requirement for instruction fetch (access requirement for instruction address or branch address) and data access requirement (access requirement for data address or physical address) cannot be processed simultaneously, one of the access requirements must be processed first when both requirements simultaneously occur. Accordingly, when the access for instruction fetch is processed first, for example, the data access requirement is in a wait state to cause a penalty.
In the conventional cache memory device in which the instruction cache and data cache are separated, there problems arise as described below upon an execution of, for example, conditional branch instruction or memory access instruction, particularly in the case applied to the RISC microprocessor supporting the multiprocessor system.
Under a construction that during the RISC microprocessor judges whether conditions of the conditional branch instruction are met in parallel with the execution of one instruction, the cache memory device processes the access requirement for instruction address from the processor, the instruction to be executed next is fetched beforehand according to a program counter when the branch conditions are not met, thus the processor can execute the next instruction immediately after it is judged that the branch conditions are not met. Since, however, the conventional cache memory device cannot simultaneously process the access requirement for instruction address and the access requirement for branch address, the branch instruction can be fetched only after the judgment of the branch conditions and process of the access requirement for instruction address are terminated. In other words, a penalty because of access for the branch instruction fetch is caused.
In addition, the conventional cache memory device in which the instruction cache and data cache are separated cannot simultaneously process the access requirement for data address based on load instruction and store instruction and the requirement for physical address for regulating the data consistency, thus one of the access requirements must be processed first upon a simultaneous occurrence thereof. Accordingly, when, for example, the access requirement for physical address is processed first, the access requirement for data address is in the wait state causing a penalty.
It is an object of the present invention to provide a cache memory device, in which instruction cache and data cache are not separated, capable of simultaneously processing at least two access requirements selected at random out of plural access requirements for instruction fetch and plural data access requirements, particularly to provide a cache memory device suitably applied to each processor unit of the multiprocessor construction including the RISC microprocessor with high access efficiency.